To optimize the electrical performance to achieve smaller appearance modeling specifications

鼎博体育's flip chip CSP (fcCSP) package is a flip chip solution in the CSP package format。This package structure is paired with our various available bump options (铜柱, lead-free solder, eutectic), realize flip chip interconnection technology in the planar array, and replace the standard welding wire interconnection in the peripheral convex block layout。The advantages of flip chip interconnection are many: it provides electrical performance superior to standard weld wire technology and eliminates the adverse effect of weld wire arcs on z-axis height by increasing wiring density。

FcCSP packages are available in laminate or molded substrates with or without core。The packaging strip process not only improves production efficiency and minimizes cost, but also enables bare crystal, cladding molding and exposed wafer structure。Integrated heat sinks manage the thermal challenges of high-power devices。Bottom-chip mount (POSSUM™) enables an in-package antenna (AiP)。Finally, with the help of copper columnar convex chips, fcCSP technology can take advantage of the advantages of small wire spacing substrate wiring and convex pitch to optimize its electrical performance while reducing the number of layers and cost。

FcCSP packages are an attractive option for applications where performance and appearance specifications are critical。For example, high-performance mobile devices (including 5G), applicable to汽车Infotainment and ADAS, as wellArtificial intelligence (ai)等。In addition, the low inductance and increased wiring density enable the optimization of the electrical path of the high frequency signal, making the fcCSP suitable for baseband, RF, and in-substrate antenna applications。


  • Suitable for low and high frequency applications
  • Low flip chip bump inductance - direct short signal channel
  • There is no technical limit on BGA balls
  • Target markets -- Mobile (AP, BB, RF, PMIC), automotive, consumer goods, connectivity, and multi-chip (stacked side by side) applications requiring high wiring density
  • Customer package size and shape based on strip process
  • Non - core, thin - core, laminate and die - sealed substrate construction
  • Bare crystal, coating molding, exposed wafer molding structure
  • Applies from 1x1 mm2To 25 x25 mm2 Package size

  • Bump pitch reduced to 50 microns (single row) and 30/60 microns (interleaved)
  • BGA ball pitch reduced to 0.3 毫米
  • Package thickness reduced to 0.35 毫米
  • One stop solution - design, bump, wafer probe, package and final test
  • Exposed wafer molding for thin thermal applications
  • Suitable for heat sink of high power components
  • Bottom chip mount for in-package antenna (AiP) applications (POSSUM™)
  • Mass reflow welding and hot compression chips

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