One-stop to meet the industry needs of WLCSP products

鼎博体育 offers wafer level chip size packages (WLCSP) that provide a direct welded interconnect between the device and the mother board of the final product。The WLCSP includes wafer chips (with or without pad rewiring layers, known as RDL), wafer level final testing, device single cutting, and coil packaging to support a complete one-stop solution。

鼎博体育's solid, bulk-underneath metal layer sits above the PBO or PI dielectric layer on the active surface of the grain, providing a reliable interconnect solution that can adapt to stringent plate level conditions and meet the growing demand for mobile electronic devices in the global consumer market。

The WLCSP package family is suitable for a variety of semiconductor device types, from high-end RF WLAN combination chips, to FPgas, power management, flash /EEPROM, integrated passive networking and standard analog and selected automotive applications。The WLCSP maximizes total cost of ownership by increasing semiconductor capacity with one of the smallest, highest performance, and most reliable semiconductor packaging solutions available today。

鼎博体育 offers three WLCSP options

  • CSPnl Repassivated layer bump (BoR) Reliable, cost-effective true chip size packages for devices that do not require rewiring。BoR uses a repassivated polymer layer with first-class electrical/mechanical properties。In addition, UBM is added and the weld bump is placed directly above the grain I/O pad。CSPnl Use industry standard surface mount assembly and reflow soldering technology。

  • CSPnl Rewiring layer convex block (RDL) The addition of an electroplated copper heavy wiring layer (RDL) to connect I/O pads to JEDEC/EIAJ standard pitch eliminates the need to redesign traditional components for CSP applications。Nickel-based or coarse copper UBM products, together with polyimide or PBO dielectric, provide the best plate level reliability performance in their class。CSPnl The RDL uses industry-standard surface bonding assembly and reflow soldering technology that eliminates the need for bottom-filling of conforming device sizes and I/O layouts。

  • CSPn3 A layer of copper surface is used in the rewiring layer and UBM。This simplified process reduces cost and cycle time by more than 20%。CSPn3 It began production in 2009 and has run more than 4 billion units since its introduction。

There is a problem?

Click the "Get Information" button at the bottom,
Contact 鼎博体育 Professionals。