The most complete flip chip package on the market
The solution

Various factors in the silicon industry are driving a surge in demand for flip chip interconnect technology。To meet this demand, 鼎博体育 is committed to becoming a major provider of flip chip packaging (FCiP) technology。By partnering with established industry leaders, 鼎博体育 is bringing its high volume packaging services to the subcontract market。As the first OSAT to offer FCiP solutions since 1999, 鼎博体育 continues to introduce innovative packaging solutions using flip chip interconnect technology and brings the most diverse FCiP solutions to market。

Flip chip interconnect offers users a number of possible advantages:

  • Reduce signal inductance-- Because the interconnect length is significantly shorter (from 1-5 mm to 0 mm).1 mm), the inductance of the signal channel is also greatly reduced。This is a key factor in high-speed communication and switching devices。
  • Reduce power/ground inductance- With flip chip interconnection, the power supply can be directly connected to the grain core, rather than having to be rewired to the edge。It can greatly reduce the noise of the core power supply and improve the performance of silicon
  • Silicon Integrated Heat sink (IHS) - Silicon integrated heat sink for fcCSP package。Because of its good thermal conductivity and simple processing, silicon can effectively replace copper as the heat sink material。The silicon integrated heat sink can be embedded in the molded interior with the top exposed and in contact with the external heat sink。

  • Higher signal densityThe entire surface of the grain can be used for interconnecting, not just the edges。This is similar to the comparison of QFP and BGA packages。Because flip chips can be connected across grain surfaces, grains of the same size support a greater number of interconnections
  • Reduced package area- In some cases, flip products can reduce the overall package area。This can be achieved by reducing the margin space required from grain to package (because there is no space reserved for the weld wire) or by using higher density substrate technology, thereby shortening the package pitch
  • Grain size reduction- The grain size can be reduced for the grain limited by the pad (the size is determined by the edge space required by the pad) to save silicon cost

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